1. Field of the Invention
The present invention relates to a high-voltage device structure. More particularly, the present invention relates to a high-voltage metal-oxide-semiconductor (HVMOS) device structure.
2. Description of the Prior Art
High-voltage metal-oxide-semiconductors are MOS devices for use under high voltages, which may be, but not limited to, voltages higher than the voltage supplied to the I/O circuit. HVMOS devices may function as switches and are broadly utilized in audio output drivers, CPU power supplies, power management systems, AC/DC converters, LCD or plasma television drivers, automobile electronic components, PC peripheral devices, small DC motor controllers, and other consumer electronic devices.
FIG. 1 is a schematic, cross-sectional view of a conventional high-voltage NMOS device. As shown in FIG. 1, the high-voltage NMOS device 101 includes a gate 210 overlying an area of a P type substrate 100, a deep N well (DNW) 110 formed in the substrate 100, an N well 120 formed in the substrate 100 proximate a first edge 210a of the gate 210 and doped with a first concentration of an N type dopant, a channel region 130 doped with a first concentration of a P type dopant underlying a portion of the gate 210 adjacent the N well 120, a shallow trench isolation (STI) region 160 formed in the first portion of the N well 120, and an N+ tap region 150 to the second portion of the N well 120 distal from the first edge 210a of the gate 210. An N type source region 155 including an N+ region and an N type lightly doped region 155b is formed in the P well 140 proximate a second edge 210b of the gate 210 opposite to the first edge 210a. 
The N+ tap region 150 is formed between the STI region 160 and the STI region 162. The N+ tap region 150 is not self-aligned with the gate 210 but is separated from the gate 210 by a distance D. The above-described high-voltage NMOS device 101 utilizes STI region 160 to drop drain voltage and makes high drain sustained voltage. Besides, the above-described high-voltage NMOS device 101 can use well implant to form drain terminal.
However, the above-described high-voltage NMOS device 101 cannot be operated when the drain is negatively biased because the junction between the DNW 110 and the P type substrate 100 will be turned on and thus causes leakage. In some circumstances, it is desirable to have a high-voltage NMOS device and the drain terminal thereof can be negatively biased.